| commit | 22983c301f01b297a6f85de4757108c6b0eac792 | [log] [tgz] |
|---|---|---|
| author | Vivek Natarajan <vnatarajan@atheros.com> | Thu Jan 27 14:45:09 2011 +0530 |
| committer | John W. Linville <linville@tuxdriver.com> | Fri Jan 28 15:44:28 2011 -0500 |
| tree | 152e76ddbdb72f82552ac02e07258df9421f0462 | |
| parent | 181fb18daaf88a20175b0da70024563b0b7c0666 [diff] |
ath9k_hw: DDR_PLL and BB_PLL need correct setting. Updates from the analog team for AR9485 chipsets to set DDR_PLL2 and DDR_PLL3. Also program the BB_PLL ki and kd value. Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>