kbuild: remove empty rules for makefiles
The previous commit made 'MAKEFLAGS += -rR' effective in the top
Makefile regardless of O= option, GNU Make versions.
The top Makefile does not need to cancel implicit rules for makefiles.
There is still one place where an empty rule is useful. Since -rR is
effective only after sub-make, GNU Make would try implicit rules to
update the top Makefile. Although it is not a big overhead, cancel it
just in case.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/Makefile b/Makefile
index db3cb73..418d205 100644
--- a/Makefile
+++ b/Makefile
@@ -37,6 +37,10 @@
# (this increases performance and avoids hard-to-debug behaviour)
MAKEFLAGS += -rR
+# 'MAKEFLAGS += -rR' does not become immediately effective for old
+# GNU Make versions. Cancel implicit rules for this Makefile.
+$(lastword $(MAKEFILE_LIST)): ;
+
# Avoid funny character set dependencies
unexport LC_ALL
LC_COLLATE=C
@@ -120,9 +124,6 @@
KBUILD_OUTPUT := $(O)
endif
-# Cancel implicit rules on top Makefile
-$(CURDIR)/Makefile Makefile: ;
-
ifneq ($(words $(subst :, ,$(CURDIR))), 1)
$(error main directory cannot contain spaces nor colons)
endif
@@ -303,8 +304,6 @@
else
-# We need some generic definitions (do not try to remake the file).
-scripts/Kbuild.include: ;
include scripts/Kbuild.include
# Read KERNELRELEASE from include/config/kernel.release (if it exists)
@@ -1760,9 +1759,7 @@
# read saved command lines for existing targets
existing-targets := $(wildcard $(sort $(targets)))
-cmd_files := $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd)
-$(cmd_files): ; # Do not try to update included dependency files
--include $(cmd_files)
+-include $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd)
endif # ifeq ($(config-targets),1)
endif # ifeq ($(mixed-targets),1)