tree 270ce13bc347fe5df0ca6d8d39f01e38b6f88213
parent b0dcfb78dc6aec8698ab5900dfdf6aeae0830815
author Joseph Lo <josephl@nvidia.com> 1546571208 +0800
committer Thierry Reding <treding@nvidia.com> 1549459721 +0100

clk: tegra: dfll: CVB calculation alignment with the regulator

The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.

When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.

Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>"
and "Alex Frid <afrid@nvidia.com>".

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>