tree 7c5fa38f885fc0ae83c1d8f944a0745f90f45bb1
parent bfeffd155283772bbe78c6a05dec7c0128ee500c
author Peter De Schrijver <pdeschrijver@nvidia.com> 1546571207 +0800
committer Thierry Reding <treding@nvidia.com> 1549459705 +0100

clk: tegra: dfll: registration for multiple SoCs

In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>