sfc_ef100: read Design Parameters at probe time
Several parts of the EF100 architecture are parameterised (to allow
varying capabilities on FPGAs according to resource constraints), and
these parameters are exposed to the driver through a TLV-encoded
region of the BAR.
For the most part we either don't care about these values at all or
just need to sanity-check them against the driver's assumptions, but
there are a number of TSO limits which we record so that we will be
able to check against them in the TX path when handling GSO skbs.
Signed-off-by: Edward Cree <ecree@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2 files changed