| commit | aba57a823d2985a2cc8c74a2535f3a88e68d9424 | [log] [tgz] |
|---|---|---|
| author | Robert Hancock <robert.hancock@calian.com> | Tue Jan 18 15:41:30 2022 -0600 |
| committer | David S. Miller <davem@davemloft.net> | Wed Jan 19 11:29:14 2022 +0000 |
| tree | ce2128ed41cdccbea07a53d5608ae4993edce4e4 | |
| parent | 996defd7f8b5dafc1d480b7585c7c62437f80c3c [diff] |
net: axienet: fix number of TX ring slots for available check
The check for the number of available TX ring slots was off by 1 since a
slot is required for the skb header as well as each fragment. This could
result in overwriting a TX ring slot that was still in use.
Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: David S. Miller <davem@davemloft.net>