| commit | a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab | [log] [tgz] |
|---|---|---|
| author | Tony Luck <tony.luck@intel.com> | Fri Mar 19 10:39:19 2021 -0700 |
| committer | Ingo Molnar <mingo@kernel.org> | Sat Mar 20 12:12:10 2021 +0100 |
| tree | e185837b47cc1d234605420fe76c7ceac8853424 | |
| parent | 301cddc21a157a3072d789a3097857202e550a24 [diff] |
x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN New CPU model, same MSRs to control and read the inventory number. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com