| commit | 9fee7563cdb535596c48e7b05383d75590a64418 | [log] [tgz] |
|---|---|---|
| author | Bharat Bhushan <Bharat.Bhushan@freescale.com> | Wed Aug 06 12:08:51 2014 +0530 |
| committer | Alexander Graf <agraf@suse.de> | Mon Sep 22 10:11:29 2014 +0200 |
| tree | ee8aba839f173d156ec4e345ac1d4b4c3556c1ba | |
| parent | f51770ed465e6eb41da7fa16fd92eb67069600cf [diff] |
KVM: PPC: BOOKE: allow debug interrupt at "debug level" Debug interrupt can be either "critical level" or "debug level". There are separate set of save/restore registers used for different level. Example: DSRR0/DSRR1 are used for "debug level" and CSRR0/CSRR1 are used for critical level debug interrupt. Using CPU_FTR_DEBUG_LVL_EXC to decide which interrupt level to be used. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>