tree 8e3e1417c7b0ece1c29d72b8333d9f16a93ded49
parent 2f1cce214b237143359202abd83575b91130260f
author Stefan Chulski <stefanc@marvell.com> 1606154073 +0200
committer Jakub Kicinski <kuba@kernel.org> 1606259104 -0800

net: mvpp2: divide fifo for dts-active ports only

Tx/Rx FIFO is a HW resource limited by total size, but shared
by all ports of same CP110 and impacting port-performance.
Do not divide the FIFO for ports which are not enabled in DTS,
so active ports could have more FIFO.
No change in FIFO allocation if all 3 ports on the communication
processor enabled in DTS.

The active port mapping should be done in probe before FIFO-init.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
Link: https://lore.kernel.org/r/1606154073-28267-1-git-send-email-stefanc@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>