| commit | 98ee8b2f66ebff2fafe85668b9d00c3433b76566 | [log] [tgz] |
|---|---|---|
| author | Biju Das <biju.das.jz@bp.renesas.com> | Fri Dec 03 11:51:49 2021 +0000 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Wed Dec 08 10:05:56 2021 +0100 |
| tree | 64135980167e655a9ff3932c2ed1ffbaedcd64bb | |
| parent | 24aaff6a6ce4c4defd18147f5078223a96283fd7 [diff] |
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree mentioned in the hardware manual(Rev.1.00 Sep, 2021). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>