| commit | 98c4b3661b5aee0e583d17d6304f6489c0f41155 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Mon Apr 20 15:05:33 2015 +0200 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Apr 28 12:41:48 2016 +0200 |
| tree | cdbb55a6cfb2d18bade67ba8ad2e876bfd743f71 | |
| parent | 3d0f4e5f7a7c9ef2d8504f2b42f9c4d3233ba707 [diff] |
clk: tegra: Add dpaux1 clock This clock is of the same type as dpaux and is added to feed into the second DPAUX block used in conjunction with SOR1. Signed-off-by: Thierry Reding <treding@nvidia.com>