| commit | 3e1f72664e0a8a31e9b90c48459deb6642fd52f3 | [log] [tgz] |
|---|---|---|
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | Fri May 03 17:23:44 2013 -0300 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Tue May 21 12:00:26 2013 +0200 |
| tree | cf20d09a07accd98b0e81f94072b9e7fd8c737bb | |
| parent | 85a02deb4ca5a7e1e39e8538b6eb3c7066469720 [diff] |
drm/i915: MCH_SSKPD is a 64 bit register on Haswell And the SNB_READ_WM0_LATENCY macro is not valid anymore because we have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if the new one is not zero. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>