| commit | 845d6b0ff92d2c8151892c81f2050b873d7a7ef7 | [log] [tgz] |
|---|---|---|
| author | Chen-Yu Tsai <wens@csie.org> | Tue Feb 14 11:35:23 2017 +0800 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Mon Mar 06 10:25:56 2017 +0100 |
| tree | 873f001cee80840bf6f9185c2aa239e01ddedf95 | |
| parent | 9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d [diff] |
clk: sunxi-ng: gate: Support common pre-dividers Some clock gates have a pre-divider between the source input and the gate itself. A notable example is the HSIC 12 MHz clock found on the A83T, which has the 24 MHz main oscillator as its input, and a /2 pre-divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>