| commit | 8041edb5920902adc9b28f2fcd9ccce395434ead | [log] [tgz] |
|---|---|---|
| author | Paul Cercueil <paul@crapouillou.net> | Wed May 08 00:17:55 2019 +0200 |
| committer | Paul Burton <paul.burton@mips.com> | Thu May 09 16:39:27 2019 -0700 |
| tree | 4de1eb98bc34c11954423c7cd176023a68e70a07 | |
| parent | 1b1f01b653b408ebe58fec78c566d1075d285c64 [diff] |
MIPS: Fix Ingenic SoCs sometimes reporting wrong ISA The config0 register in the Xburst CPUs with a processor ID of PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, but they don't actually support this ISA. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org