| commit | ae9ec62bdadc4cd3bf893d6baced80aa3a5dbbd6 | [log] [tgz] |
|---|---|---|
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | Tue Mar 15 16:40:05 2016 +0200 |
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | Tue Apr 12 21:12:02 2016 +0300 |
| tree | 97329e1675016aa44a43ebb7eccbb378ff473e35 | |
| parent | f00b56896ec2443a33277f5411de0cbd13071cec [diff] |
drm/i915: Fix CHV DSI PLL refclk during state readout Use the proper refclock frequency (100MHz) when reading out the current DSI clock on CHV. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458052809-23426-13-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>