tree 57430fc906fc301e499c2beadb8df75b1c6f50be
parent 2a58fca9a7b4a3953c3e983ef80e36df85293a7c
author Philip Elcan <pelcan@codeaurora.org> 1522202132 -0400
committer Will Deacon <will.deacon@arm.com> 1522246817 +0100

arm64: tlbflush: avoid writing RES0 bits

Several of the bits of the TLBI register operand are RES0 per the ARM
ARM, so TLBI operations should avoid writing non-zero values to these
bits.

This patch adds a macro __TLBI_VADDR(addr, asid) that creates the
operand register in the correct format and honors the RES0 bits.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Philip Elcan <pelcan@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>