| commit | 7ede12b01b59dc67bef2e2035297dd2da5bfe427 | [log] [tgz] |
|---|---|---|
| author | David Abdurachmanov <david.abdurachmanov@sifive.com> | Sat Jun 12 17:43:57 2021 -0700 |
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | Sat Jun 19 00:11:53 2021 -0700 |
| tree | dcf04066281ea4fbbcc7db709bf462862fde2d69 | |
| parent | 3a02764c372c50ff7917fde5c6961f6cdb81d9d5 [diff] |
riscv: dts: fu740: fix cache-controller interrupts The order of interrupt numbers is incorrect. The order for FU740 is: DirError, DataError, DataFail, DirFail From SiFive FU740-C000 Manual: 19 - L2 Cache DirError 20 - L2 Cache DirFail 21 - L2 Cache DataError 22 - L2 Cache DataFail Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>