| commit | 7dbc7f5f4904cfddc199af171ea095490a434f15 | [log] [tgz] |
|---|---|---|
| author | Jernej Škrabec <jernej.skrabec@siol.net> | Sat Dec 30 22:01:54 2017 +0100 |
| committer | Chen-Yu Tsai <wens@csie.org> | Wed Jan 03 13:45:04 2018 +0800 |
| tree | 0e8b3a79fe339717b8aea4ceae21e479576f7877 | |
| parent | cf4881c1293516c1975606e8f2af7948789168b8 [diff] |
clk: sunxi-ng: a83t: Add M divider to TCON1 clock
TCON1 also has M divider, contrary to TCON0. And the mux is only
2 bits wide, instead of 3.
Fixes: 05359be1176b ("clk: sunxi-ng: Add driver for A83T CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
[wens@csie.org: Add description about mux width difference]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>