tree ec9c76dd91f151646a32b5b4252e9f1cb2a06de4
parent e53111ad5deaef98d8c18a9933ef1f5624c5979d
author Martin Blumenstingl <martin.blumenstingl@googlemail.com> 1509480103 +0100
committer Jonathan Cameron <Jonathan.Cameron@huawei.com> 1512213313 +0000

iio: adc: meson-saradc: fix the bit_idx of the adc_en clock

Meson8 and Meson8b SoCs use the the SAR ADC gate clock provided by the
MESON_SAR_ADC_REG3 register within the SAR ADC register area.
According to the datasheet (and the existing MESON_SAR_ADC_REG3_CLK_EN
definition) the gate is on bit 30.
The fls() function returns the last set bit, which is "bit index + 1"
(fls(MESON_SAR_ADC_REG3_CLK_EN) returns 31). Fix this by switching to
__ffs() which returns the first set bit, which is bit 30 in our case.

This off by one error results in the ADC not being usable on devices
where the bootloader did not enable the clock.

Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>