tree 7cdb253aad9b75c1f3cc711b4fcabbe445057909
parent 49b7cb5da1867511f10ca9fb7be44c0b2c6a79ee
author Nikhil Devshatwar <nikhil.nd@ti.com> 1430833799 -0300
committer Mauro Carvalho Chehab <mchehab@osg.samsung.com> 1433586424 -0300

[media] v4l: of: Correct pclk-sample for BT656 bus

Current v4l2_of_parse_parallel_bus function attempts to parse the
DT properties for the parallel bus as well as BT656 bus.
If the pclk-sample property is defined for the BT656 bus, it is still
marked as a parallel bus.
Fix this by parsing the pclk after the bus_type is selected.
Only when hsync or vsync properties are specified, the bus_type should
be set to V4L2_MBUS_PARALLEL.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>