| commit | 6b76bcc004b046ea3c8eb66bbc6954f1d23cc2af | [log] [tgz] |
|---|---|---|
| author | Sugar Zhang <sugar.zhang@rock-chips.com> | Thu Aug 26 12:01:48 2021 +0800 |
| committer | Mark Brown <broonie@kernel.org> | Thu Aug 26 13:59:31 2021 +0100 |
| tree | e456bf342072a723076a8b77880a3c2281fbd217 | |
| parent | ebfea67125767a779af63ae6de176709713c8826 [diff] |
ASoC: rockchip: i2s: Fixup clk div error MCLK maybe not precise as required because of PLL, but which still can be used and no side effect. so, using DIV_ROUND_CLOSEST instead div. e.g. set mclk to 11289600 Hz, but get 11289598 Hz. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Link: https://lore.kernel.org/r/1629950520-14190-2-git-send-email-sugar.zhang@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>