tree de6730ff106e00742ab025e5f3ab233db7c1d6ca
parent 77d57d1d8016696daaf5614c070ac01c9652f4ce
author Dmitry Osipenko <digetx@gmail.com> 1559588382 +0300
committer Daniel Lezcano <daniel.lezcano@linaro.org> 1561484958 +0200

clocksource/drivers/tegra: Replace readl/writel with relaxed versions

The readl/writel functions are inserting memory barrier to ensure that
outstanding memory writes are completed, this results in L2 cache syncing
being done on Tegra20 and Tegra30 which isn't a very cheap operation.
Replace all readl/writel occurrences in the code with the relaxed versions
since there is no need for the memory-access syncing.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>