tree 3d68d10c95ed7d87fd1692448e3903b801b40e94
parent f252ffd50c97dae87b45f1dbad24f71358ccfbd6
author David Daney <ddaney@caviumnetworks.com> 1262999864 -0800
committer Ralf Baechle <ralf@linux-mips.org> 1267271586 +0100

MIPS: Octeon: Use optimized memory barrier primitives.

In order to achieve correct synchronization semantics, the Octeon port
had defined CONFIG_WEAK_REORDERING_BEYOND_LLSC.  This resulted in code
that looks like:

   sync
   ll ...
   .
   .
   .
   sc ...
   .
   .
   sync

The second SYNC was redundant, but harmless.

Octeon has a SYNCW instruction that acts as a write-memory-barrier
(due to an erratum in some parts two SYNCW are used).  It is much
faster than SYNC because it imposes ordering on the writes, but
doesn't otherwise stall the execution pipeline.  On Octeon, SYNC
stalls execution until all preceeding writes are committed to the
coherent memory system.

Using:

    syncw;syncw
    ll
    .
    .
    .
    sc
    .
    .

Has identical semantics to the first sequence, but is much faster.
The SYNCW orders the writes, and the SC will not complete successfully
until the write is committed to the coherent memory system.  So at the
end all preceeding writes have been committed.  Since Octeon does not
do speculative reads, this functions as a full barrier.

The patch removes CONFIG_WEAK_REORDERING_BEYOND_LLSC, and substitutes
SYNCW for SYNC in write-memory-barriers.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/850/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>