| commit | 68fe2b520cee829ed518b4b1f64d2a557bcbffe1 | [log] [tgz] |
|---|---|---|
| author | Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> | Thu Sep 26 16:20:57 2019 +0530 |
| committer | Vinod Koul <vkoul@kernel.org> | Tue Oct 15 15:41:55 2019 +0530 |
| tree | 6cbe57e6d548617343d316b84a45c1e5601c067b | |
| parent | bd73dfabdda280fc5f05bdec79b6721b4b2f035f [diff] |
dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer In AXI DMA simple mode also pass MSB bits of source and destination address to xilinx_write function. It fixes simple AXI DMA operation mode using 64-bit addressing. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1569495060-18117-2-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>