tree 87615147b69008ac30cfcff53765d749fc73e979
parent accf475a5ece972af58c81e0742035ed90ad41d2
author Benjamin Herrenschmidt <benh@kernel.crashing.org> 1515736081 +1100
committer Stephen Boyd <sboyd@codeaurora.org> 1517012568 -0800

clk: aspeed: Handle inverse polarity of USB port 1 clock gate

The USB port 1 clock gate control has an inversed polarity
from all the other clock gates in the chip. This makes the
aspeed_clk_{enable,disable} functions honor the flag
CLK_GATE_SET_TO_DISABLE and set that flag appropriately
so it's set for all clocks except USB port 1.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>