| commit | 651d1f2040ac46d87c67cfe512bbd7668c34fec6 | [log] [tgz] |
|---|---|---|
| author | Daniel Scally <djrscally@gmail.com> | Tue Nov 23 01:00:04 2021 +0100 |
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | Tue Nov 30 10:52:35 2021 +0100 |
| tree | a3c80cc440469a2e597486bdcb5644a70f992892 | |
| parent | dc69bc7a2e09791d8466202a5b10b14400191116 [diff] |
media: i2c: Fix incorrect value in comment The PLL configuration defined here sets 72MHz (which is correct), not 80MHz. Correct the comment. Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Daniel Scally <djrscally@gmail.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>