| commit | 6241bf6a59a41c7ca742c043416b6d57109c6b5d | [log] [tgz] |
|---|---|---|
| author | Felix Fietkau <nbd@nbd.name> | Mon May 16 19:51:54 2016 +0200 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Tue May 17 11:12:38 2016 +0200 |
| tree | bb03d4a5c0d9d2fb30bcb8cbd6fe13fe237b2643 | |
| parent | bad50d79255a8a479ea63bea89e859bf08fd0f24 [diff] |
MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs AR913x, AR724x and AR933x are the only SoCs where the ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c Invert the logic to make the code compatible with AR95xx Signed-off-by: Felix Fietkau <nbd@nbd.name> Cc: albeu@free.fr Cc: sergei.shtylyov@cogentembedded.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13257/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>