tree a63664a71dcba97d57a0604dadd381c21493b9a6
parent 093e3f134e2eff13503f708b81aecc2501e7aecb
author Ville Syrjälä <ville.syrjala@linux.intel.com> 1413484054 +0300
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1415139721 +0100

drm/i915: Wait for PHY port ready before link training on VLV/CHV

There's no point in checking if the data lanes came out of reset after
link training. If the data lanes aren't ready link training will fail
anyway.

Suggested-by: Todd Previte <tprevite@gmail.com>
Cc: Todd Previte <tprevite@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Acked-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>