| commit | 5dcef694860100fd16885f052591b1268b764d21 | [log] [tgz] |
|---|---|---|
| author | Len Brown <len.brown@intel.com> | Wed Apr 06 17:00:47 2016 -0400 |
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | Sat Apr 09 02:17:43 2016 +0200 |
| tree | 7c083237a14697091466b2506f039e8d45363daa | |
| parent | c998c07836f985b24361629dc98506ec7893e7a0 [diff] |
intel_idle: add BXT support Broxton has all the HSW C-states, except C3. BXT C-state timing is slightly different. Here we trust the IRTL MSRs as authority on maximum C-state latency, and override the driver's tables with the values found in the associated IRTL MSRs. Further we set the target_residency to 1x maximum latency, trusting the hardware demotion logic. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>