commit 5b792d320f28ff83dd4c13f984807e26235f7703
author Randy Dunlap <randy.dunlap@oracle.com> Thu Aug 21 13:43:51 2008 -0700
committer Ingo Molnar <mingo@elte.hu> Fri Aug 22 06:55:21 2008 +0200
tree 51681747d4c731f1ca1b5ba7f6c8b763e0edb41e
parent d45de40934897c6ee5b05141f7895bbb28512395

x86, microcode_amd: fix shift warning

microcode_amd.c uses ">> 32" on a 32-bit value, so gcc warns about that.
The code could use something like this *untested* patch.

linux-next-20080821/arch/x86/kernel/microcode_amd.c:229: warning: right shift count >= width of type

Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

arch/x86/kernel/microcode_amd.c

diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 4006e5e..d606a05 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -206,6 +206,7 @@
 	unsigned int rev;
 	int cpu_num = raw_smp_processor_id();
 	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
+	unsigned long addr;
 
 	/* We should bind the task to the CPU */
 	BUG_ON(cpu_num != cpu);
@@ -215,10 +216,9 @@
 
 	spin_lock_irqsave(&microcode_update_lock, flags);
 
-	edx = (unsigned int)(((unsigned long)
-			      &(uci->mc.mc_amd->hdr.data_code)) >> 32);
-	eax = (unsigned int)(((unsigned long)
-			      &(uci->mc.mc_amd->hdr.data_code)) & 0xffffffffL);
+	addr = (unsigned long)&uci->mc.mc_amd->hdr.data_code;
+	edx = (unsigned int)(((unsigned long)upper_32_bits(addr)));
+	eax = (unsigned int)(((unsigned long)lower_32_bits(addr)));
 
 	asm volatile("movl %0, %%ecx; wrmsr" :
 		     : "i" (0xc0010020), "a" (eax), "d" (edx) : "ecx");