tree 77aecfaf248bc4f2fe048e7a9ae1d51fd579cd18
parent faacc290eeaf28f24a2ff5cb1ec033e6c9f3811d
author Dirk Behme <dirk.behme@de.bosch.com> 1366964035 +0200
committer Shawn Guo <shawn.guo@linaro.org> 1371456260 +0800

ARM: dts: i.MX6: configure L2 cache data and tag latency

Configure the data and tag latency for the L2 cache. This improves the
system performance.

This configuration is taken from Freescale's kernel patch

"ENGR00153601 [MX6]Adjust L2 cache parameter" [1]

which does

writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));

In this patch we are doing the same via the device tree.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

[1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1