| commit | 58c0f79887d5e425fe6a9fd542778e50df69e9c6 | [log] [tgz] |
|---|---|---|
| author | Rongyi Chen <chenyi@tt-cool.com> | Fri Aug 10 23:16:38 2018 +0800 |
| committer | Chen-Yu Tsai <wens@csie.org> | Mon Aug 27 10:35:04 2018 +0800 |
| tree | 6de7e85a2f62c31958b4f130647a5d84fc230200 | |
| parent | 2852bfbf4f168fec27049ad9ed20941fc9e84b95 [diff] |
clk: sunxi-ng: h6: fix PWM gate/reset offset
Currently the register offset of the PWM bus gate in Allwinner H6 clock
driver is wrong.
Fix this issue.
Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Rongyi Chen <chenyi@tt-cool.com>
[Icenowy: refactor commit message]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>