tree 638ffc11b6bfcfc706763b7b6c51fc99b8e84819
parent 30a970c6a6ff734eda7cefe7e88f030157a6c939
author Jesse Barnes <jbarnes@virtuousgeek.org> 1383610019 -0800
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1383676127 +0100

drm/i915/vlv: split CCK and DDR freq usage

It's possible that the CCK clock could run at a different rate than the
DDR clock, so use the same method to get CCK as the GMBUS code does when
calculating the new CDclk divider in the VLV display code.

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>