| commit | 573803234e72d182ec39692770110e574cd5b222 | [log] [tgz] |
|---|---|---|
| author | Rick Altherr <raltherr@google.com> | Tue Mar 28 14:52:59 2017 -0700 |
| committer | Jonathan Cameron <jic23@kernel.org> | Sat Apr 01 11:53:20 2017 +0100 |
| tree | 9c4dfe0ff91e55844e8d48f5ff605b33149ae793 | |
| parent | fb87ecf19e350d73206c5fbf28a28588f171f15d [diff] |
iio: Aspeed ADC Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold interrupts are supported by the hardware but are not currently implemented. Signed-off-by: Rick Altherr <raltherr@google.com> Tested-by: Xo Wang <xow@google.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Jonathan Cameron <jic23@kernel.org>