commit 4e03f628b464e0580abadf5161eaa38c61d20943
author Masahiro Yamada <yamada.masahiro@socionext.com> Tue Feb 14 20:05:40 2017 +0900
committer Ulf Hansson <ulf.hansson@linaro.org> Wed Feb 15 11:32:14 2017 +0100
tree 6d929f2c69d9bd4f725c2bb3266e2400d1b8224e
parent 006cac8262987981fb10a0360726875b48123b73

mmc: sdhci-cadence: fix bit shift of read data from PHY port

This macro is currently unused, but it may be useful for debug use.
Fix it just in case.

Fixes: ff6af28faff5 ("mmc: sdhci-cadence: add Cadence SD4HC support")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

drivers/mmc/host/sdhci-cadence.c

diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 31e786d..316cfec 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -26,7 +26,7 @@
 #define   SDHCI_CDNS_HRS04_ACK			BIT(26)
 #define   SDHCI_CDNS_HRS04_RD			BIT(25)
 #define   SDHCI_CDNS_HRS04_WR			BIT(24)
-#define   SDHCI_CDNS_HRS04_RDATA_SHIFT		12
+#define   SDHCI_CDNS_HRS04_RDATA_SHIFT		16
 #define   SDHCI_CDNS_HRS04_WDATA_SHIFT		8
 #define   SDHCI_CDNS_HRS04_ADDR_SHIFT		0