tree 557a64c93cb81f78c1c07e40f74c213006822709
parent 44edff1bbc48595a041f65a725203763e3590a73
author Daniel Kurtz <djkurtz@chromium.org> 1520873130 -0600
committer Linus Walleij <linus.walleij@linaro.org> 1522055389 +0200

pinctrl/amd: poll InterruptEnable bits in enable_irq

In certain cases interrupt enablement will be delayed relative to when
the InterruptEnable bits are written.  One example of this is when
a GPIO's "debounce" logice is first enabled.  After enabling debounce,
there is a 900 us "warm up" period during which InterruptEnable[0]
(bit 11) will read as 0 despite being written 1.  During this time
InterruptSts will not be updated, nor will interrupts be delivered, even
if the GPIO's interrupt configuration has been written to the register.

To work around this delay, poll the InterruptEnable bits after setting
them to ensure interrupts have truly been enabled in hardware before
returning from the irq_enable handler.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>