| commit | 3c1dae0a07c651526f8e878d223a88f82caa5a50 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Thu Jun 11 18:33:48 2015 +0200 |
| committer | Thierry Reding <treding@nvidia.com> | Fri Jun 12 16:22:46 2015 +0200 |
| tree | c71bc338728059b18bfd0f031956fbb73e288751 | |
| parent | b787f68c36d49bb1d9236f403813641efa74a031 [diff] |
drm/tegra: dpaux: Fix transfers larger than 4 bytes
The DPAUX read/write FIFO registers aren't sequential in the register
space, causing transfers larger than 4 bytes to cause accesses to non-
existing FIFO registers.
Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support")
Signed-off-by: Thierry Reding <treding@nvidia.com>