| commit | 44991eb4bfd63b043b50e880d347a7946d6a9736 | [log] [tgz] |
|---|---|---|
| author | Jisheng Zhang <jszhang@marvell.com> | Thu Jun 12 17:38:40 2014 +0800 |
| committer | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | Mon Jun 16 13:09:04 2014 +0200 |
| tree | 8fcacf5483a5efe8b605521867cdbc72fc1c3ede | |
| parent | 7171511eaec5bf23fb06078f59784a3a0626b38f [diff] |
ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles For all BG2Q SoCs, 2 cycles is the best/correct value. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>