| commit | 44275932589a84a24849290b0d5c22157016a5e6 | [log] [tgz] |
|---|---|---|
| author | Radim Krčmář <rkrcmar@redhat.com> | Fri Oct 06 19:25:55 2017 +0200 |
| committer | Paolo Bonzini <pbonzini@redhat.com> | Thu Oct 12 14:01:54 2017 +0200 |
| tree | 057272d4093341735845152b4da89d5b05a76bbd | |
| parent | 5d74a6999368ad1991491b1913bb80faf1925e67 [diff] |
KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch Our routines look at tscdeadline and period when deciding state of a timer. The timer is disarmed when switching between TSC deadline and other modes, so we should set everything to disarmed state. Signed-off-by: Radim Krčmář <rkrcmar@redhat.com> Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>