commit | 410066d24cfc1071be25e402510367aca9db5cb6 | [log] [tgz] |
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author | Jake Wang <haonan.wang2@amd.com> | Thu Dec 03 14:05:56 2020 -0500 |
committer | Alex Deucher <alexander.deucher@amd.com> | Tue Dec 15 11:34:23 2020 -0500 |
tree | 038fbe2ddbd2eb466601e15face761b05f830db8 | |
parent | 5200c4017ef25f85634012a967c78ff64495dd85 [diff] |
drm/amd/display: updated wm table for Renoir [Why] For certain timings, Renoir may underflow due to sr exit latency being too slow. [How] Updated wm table for renoir. Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>