| commit | 4097c9a64d1009d97dcee772bd8b15381bc7507d | [log] [tgz] |
|---|---|---|
| author | Tony Lindgren <tony@atomide.com> | Mon Nov 16 12:57:13 2020 +0200 |
| committer | Tony Lindgren <tony@atomide.com> | Mon Nov 16 12:57:15 2020 +0200 |
| tree | a5af6a20512a4a31ae75acf641ea038e8cc3f532 | |
| parent | c1995e5afaf6abf3922b5395ad1f4096951e3276 [diff] |
bus: ti-sysc: Assert reset only after disabling clocks The rstctrl reset must be asserted after gating the module clock as described in the TRM at least for IVA. Otherwise the rstctrl reset done with module clock enabled can hang the system. Note that this issue is has been only seen with related IVA changes that we do not currently have merged. So probably no need to apply this patch as a fix. Signed-off-by: Tony Lindgren <tony@atomide.com>