| commit | 3ff46fd0b22abbb8d921d7e5657912bfbd41b6f0 | [log] [tgz] |
|---|---|---|
| author | Dmitry Osipenko <digetx@gmail.com> | Wed Oct 04 02:02:39 2017 +0300 |
| committer | Thierry Reding <treding@nvidia.com> | Wed Nov 01 15:00:04 2017 +0100 |
| tree | e2a7e4414151d8d37502ab06abbc5d28cabf482f | |
| parent | 899f8095e66c562888ff617686e46019b758611b [diff] |
clk: tegra: Correct parent of the APBDMA clock APBDMA represents a clock gate to the APB DMA controller, the actual clock source for the controller is PCLK. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>