| commit | 3d5155eaadaf512808cb57ec0c7db7bd4cc1ef67 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Thu May 17 11:04:15 2018 +0200 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Tue Jun 19 10:19:51 2018 +0200 |
| tree | b552e62b9222acd545013611a84241122220d836 | |
| parent | ce397d215ccd07b8ae3f71db689aedb85d56ab40 [diff] |
clk: renesas: r8a7795: Add CR clock Add the CR core clock, which is used by the Secure Engine (SCEG). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Gilad Ben-Yossef <gilad@benyossef.com>