| commit | 3bd4f277274bd7dde65879e5c8cd16d0b34eba90 | [log] [tgz] |
|---|---|---|
| author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | Tue Jun 19 14:23:21 2018 +0300 |
| committer | Wolfram Sang <wsa@the-dreams.de> | Tue Jul 03 23:05:35 2018 +0200 |
| tree | ab00e44111170c8f833ccb0144496c4dfbdfab72 | |
| parent | 83b2cb48cbc5c4196fcc9357836f30713f74dbc2 [diff] |
i2c: designware: Call i2c_dw_clk_rate() only once in i2c_dw_init_master() This is rather readability update than micro-optimization, or if not optimization at all. We take the input clock rate to a variable and pass that to SCL timing parameter calculation functions. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>