| commit | 38555434a910a657ba6d7d06a4fe0376c8b04685 | [log] [tgz] |
|---|---|---|
| author | Nicholas Piggin <npiggin@gmail.com> | Tue Feb 26 18:51:10 2019 +1000 |
| committer | Michael Ellerman <mpe@ellerman.id.au> | Tue Feb 26 23:28:26 2019 +1100 |
| tree | cd1b893915eff74c542d57bc3187e59bebdf22cb | |
| parent | e779fc93643c1181b0164745a537986a525850ca [diff] |
powerpc/64s: Fix data interrupts vs d-side MCE reentrancy Handlers for interrupts that set DAR / DSISR, set MSR[RI] before those SPRs are read. If a d-side machine check hits in this window, DAR / DSISR will be clobbered silently, leading to random corruption. Fix this by having handlers save those registers before setting MSR[RI]. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>