| commit | 38389aa6ba82b8d598fdb02f8907eca132ec2c1b | [log] [tgz] |
|---|---|---|
| author | Grygorii Strashko <grygorii.strashko@ti.com> | Fri Jun 26 21:17:09 2020 +0300 |
| committer | David S. Miller <davem@davemloft.net> | Mon Jun 29 17:06:19 2020 -0700 |
| tree | adc2ecf4f16e92f498a027e098b334d12ed5ca32 | |
| parent | 3d0fda901c058844bcd72bc6098c6c86884d1877 [diff] |
net: ethernet: ti: am65-cpsw-nuss: enable am65x sr2.0 support The AM65x SR2.0 MCU CPSW has fixed errata i2027 "CPSW: CPSW Does Not Support CPPI Receive Checksum (Host to Ethernet) Offload Feature". This errata also fixed for J271E SoC. Use SOC bus data for K3 SoC identification and apply i2027 errata w/a only for the AM65x SR1.0 SoC. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>