tree 34853a8f289d56d5dff02f18975aa0e2fbb8b84d
parent 0a87bf6cd5297d8ae99f3560a7969a0b141f7350
author Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> 1535832748 +0300
committer Geert Uytterhoeven <geert+renesas@glider.be> 1535961513 +0200

clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI

On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2
SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver.
We'll also need to support the SoC specific clock types, thus we're adding
CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare
SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in
the overridden cpg_clk_register() method; then, finally, add the SD-IF
module clock (derived from the SD0 clock).

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>