tree 1516d43b7b33e03f8b531552764a3e8406dde8bf
parent 02a5417751c31cd64197652c000a5ab0d3261465
author Ralf Baechle <ralf@linux-mips.org> 1350418386 +0200
committer Ralf Baechle <ralf@linux-mips.org> 1350418943 +0200

MIPS: R5000: Fix TLB hazard handling.

R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and
RM5271) are basically the same CPU core and all are documented to require
two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0,
c0_entrylo1 or c0_index.

So far we were only providing on cycle before / after a TLBR/TLBWI
for R5000 but 3 cycles before and 1 cycles after for the Nevadas.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>