| commit | 32cae024f7186e60cbdeb5b594eb920036f38225 | [log] [tgz] |
|---|---|---|
| author | Abhishek Sahu <absahu@codeaurora.org> | Wed Dec 13 19:55:34 2017 +0530 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Thu Dec 21 16:03:26 2017 -0800 |
| tree | 60c329621e6f73ada01bf8288db2232bb0810d01 | |
| parent | df964016490b2cf630b1b926a1d5c610833aaa84 [diff] |
clk: qcom: ipq8074: fix missing GPLL0 divider width GPLL0 uses 4 bits post divider which should be specified in clock driver structure. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>