| commit | 2f13eb7c580fcbe3d73ebbe6fb1841381cad0a05 | [log] [tgz] |
|---|---|---|
| author | Sohil Mehta <sohil.mehta@intel.com> | Wed Dec 20 11:59:27 2017 -0800 |
| committer | Joerg Roedel <jroedel@suse.de> | Wed Jan 17 15:02:50 2018 +0100 |
| tree | 9c8c8de8d4b40a3b81e8515f1baef0ac72f1c4bd | |
| parent | f1ac10c24efbbcba0f8dae37ee90d45847f5c5af [diff] |
iommu/vt-d: Enable 5-level paging mode in the PASID entry If the CPU has support for 5-level paging enabled and the IOMMU also supports 5-level paging then enable the 5-level paging mode for first- level translations - used when SVM is enabled. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>